ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output frequency range: 8.33 MHz to 200 MHz Input frequency range: 6.25 MHz to 125 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ±2% max .

Block Diagram XIN XOUT VCO_SEL PLL_EN REF_SEL 0 TCLK0 TCLK1 TCLK_SEL FB_IN 0 1 LPF D Q Sync Frz QB0 QB1 QB2 QB3 MR#/O.

The ASM5I9772A is a low-voltage high-performance 200 MHz PLL-based zero delay buffer, designed for highspeed clock-distribution applications. Block Diagram XIN XOUT VCO_SEL PLL_EN REF_SEL 0 TCLK0 TCLK1 TCLK_SEL FB_IN 0 1 LPF D Q Sync Frz QB0 QB1 QB.

ASM5I9773A

ASM5I9774A

ASM5I9775A

ASM5I9350

ASM5I9351

ASM5I9352

ASM5I961C

ASM5I961P

ASM5I9653A

ASM5I9658

ASM5I2304A

ASM5I2304B

ASM5I2305A

Since 2006. D4U Semicon.   |   Contact Us   |   Privacy Policy   |   Purchase of parts